module sig_gen#(
    parameter integer CNT_WIDTH = 32
)(
    input sys_clk,
    input rst_n,
    input [CNT_WIDTH - 1:0] div_factor,
    output reg sig_o
);

reg [CNT_WIDTH - 1:0] r_cnt;

always @(posedge sys_clk, negedge rst_n) begin
    if (~rst_n) begin
        r_cnt <= 0;
    end else if (r_cnt >= div_factor) begin
        r_cnt <= 0;
    end else begin
        r_cnt <= r_cnt + 1'b1;
    end
end

always @(posedge sys_clk, negedge rst_n) begin
    if (~rst_n) begin
        sig_o <= 1'b0;
    end else if (r_cnt >= div_factor) begin
        sig_o <= ~sig_o;
    end
end

endmodule
